Front End Design Engineer

About the role

Designs hardware tasks for AI models, using RTL, synthesis, and verification tools to create accurate benchmarks for digital design.

Skills

• Verilog must have
• SystemVerilog must have
• Cadence Genus must have
• Synopsys Design Compiler must have
• AMD Vivado must have
• Yosys must have
• Icarus Verilog must have
• Verilator must have
• cocotb must have
• Python must have