Senior Solution Architect

About the role

Leads the full-chip physical design lifecycle for high-performance SoCs, ensuring optimal Power, Performance, and Area (PPA) on advanced process nodes.

Skills

• Synopsys (Fusion Compiler, IC Compiler II, PrimeTime, StarRC, VC LP) must have
• Cadence (Innovus, Tempus, Quantus, Pegasus, Voltus) must have
• TCL must have
• Python must have
• Shell must have
• Static Timing Analysis (STA) must have
• Electromigration and IR Drop (EMIR) must have
• Low Power Compliance (VCLP/UPF) must have
• Physical Verification (DRC/LVS/ERC) must have
• Clock Tree Synthesis (CTS) must have