Lead Design Engineer ( Synthesis/LEC/CLP ) interview practice at Semiconductor.Cv
40 questions · 40 minutes · ₹25
What it covers
- Cadence Genus
- Conformal (LEC and/or CLP)
- UPF/CPF-based power intent (IEEE 1801)
- Tcl
- Perl
- Python
- Digital design fundamentals
- STA basics
- Low-power architecture concepts
- Lead Design Engineer ( Synthesis/LEC/CLP ) fundamentals
- Projects on your CV